In dynamic random access memories (DRAMs), the memory cells need to be periodically restored (also referred to as refreshed). This is achieved as part of the sensing operation. A DRAM typically has a multiplexed address. The row address occurs first and selects a word line which is to be enabled. Each memory cell coupled to the enabled word line outputs data contained in the memory cell onto a bit line to which it is coupled which in turn is coupled to a sense amplifier. There are actually two bit lines coupled to each sense amplifier. One bit line is coupled to an enabled memory cell. The other bit line is used as a reference. This bit line used a reference has often had a reference or dummy cell connected to it. Another technique has left the reference bit line floating. In either case a voltage differential is developed between the bit line with the enabled cell and the reference bit line which is amplified by a sense amplifier. The sense amplifier increases the voltage separation of the two bit lines. The sense amplifier actually provides the refresh of the enabled memory cell. For the memory cell to be refreshed, the word line must be enabled and the bit line which is coupled to the enabled memory cell should be at as near the power supply as possible, i.e., 5 volts or ground, depending on the logic state which is to be restored.
The time required for the bit lines to become fully separated is longer than that required just for determining the logic state stored by the memory cell. Additionally, the selected bit line is not brought to full power supply voltage while the column decoder is coupling it to a secondary amplifier. Consequently, a full restore may not occur for the memory cell which was selected to be read. To reduce the loading on a selected bit line, the conductivity of the column decoder coupling transistors which coupled the bit lines to the secondary amplifier was decreased. This had the beneficial effect of allowing the sense amplifier to more nearly bring the bit line with the selected memory cell to the power supply voltage. There was, however, a disadvantage. The increased resistance of the column decoder couplng transistors reduced the speed with which a read or a write could be accomplished. Consequently, a tradeoff between speed and restore had to be made.